As the dimensions (line widths) of integrated circuits continue to decrease, the planarization of a semiconductor architecture continues to be critical to the successful formation of its topographical features, such as trench isolation and one or more layers of (polysilicon) interconnect. For example, polysilicon is typically non-selectively deposited and then selectively etched to form a prescribed conductor pattern on the surface of semiconductor structure. If the surface on which the polysilicon is deposited is not planar, then, after a selective etch, any polysilicon that remains in uneven areas of the non-planar surface, such as in depressions or alongside high aspect ratio mesa regions, may form unwanted `stringers` that extend over and undesirably interconnect or effectively short together two or more portions of the integrated circuit structure.
Additionally, if the surface level of the trench fill oxide is below the surface of its adjacent mesa structure, a conductive layer that overlies the trench fill oxide and is to be formed on a thin (e.g. gate) insulator layer terminating at the trench edge may be shorted to the underlying mesa material just below the lip of the trench. Of course, since the depth of focus of photolithographic equipment is limited, it is essential that the topography of the structure be as planar as possible in order to accurately image a given circuit pattern on the semiconductor surface to be processed.
One proposed methodology for planarizing the surface of an oxide-filled, trench-isolation semiconductor architecture, such as that described, for example, in an article by T. H. Daubenspeck et al, entitled "Planarization of ULSI Topography over Variable Pattern Densities," Journal of the Electrochemical Society, Vol. 138, No.2, February 1991, pp 506-509 involves `ideally` defining the composition of the etch chemistry, so as to equalize the etch rate of a sacrificial photoresist layer and the etch rate of oxide material contiguous with the photoresist material. We have found, however, that such a process is very unstable, being sensitive to the history of the operation of the etching chamber, so that the chamber would have to be seasoned in order to maintain the desired etch rate balance. Unfortunately, however, it turns out that seasoning the etching chamber is not an effective solution, since the original seasoning becomes degraded and is continuously modified as the conditions within the chamber change during the process. In particular, the original chamber chemistry that has been prepared for a global one-to-one etch rate of photoresist and oxide designed process becomes locally sensitive to the loading effect of oxide, which causes photoresist to be etched more rapidly than the oxide, thereby creating an undulating surface contour.
Another proposed technique uses a complicated series of etch steps that are intended to maintain an optimum (ideally one-to-one) etch selectivity to correct for loading effects, or by flowing either a photoresist plug, or a flowable oxide film (e.g. SOG OR BPSG) in valleys of the undulating surface of the oxide in an attempt to create a final planarized overlay. A principal disadvantage of this process is the need to develop etch chemistries that can maintain a prescribed etch rate selectivity to diverse composition portions of the planarization overlay being etch (e.g. photoresist (PR) vs. BPSG), PR vs. SOG, BPSG vs. USG, etc.). Moreover manufacturability of the process is extremely sensitive to the repeatability of prior processes carried out in the etch chamber.
Still another suggested scheme simply overfills the trench with non-selectively deposited oxide and then relies on plasma smoothing to remove the final fill material in an attempt to remove or decrease any `grooving` of the trench oxide fill. However, long exposure times of `seamed` oxides tend to exaggerate, rather than lessen, groove formation.
In addition to the problems discussed above, traditional planarization processes which employ a batch reactor suffer from typical batch reactor nonuniformities, which produce device yield losses for both under etched and overetched regions of the semiconductor structure.